According to our sources, the 512 Bit version of the AVX SIMD will be fully enabled only on SkyLake Xeon models. The consumer part, the “Core” models, will have AVX-512 SIMD disabled.
This means that SkyLake “Core” will be not so much different than Haswell “Core” about the supported SIMDs (see the table below), and just the professional users will be able to take advantage of AVX-512 set instructions. Only with Cannonlake will we see the AVX-512 SIMD on “Core” models, during 2016/2017 (if we are lucky: Intel is already studying a Refresh version of SkyLake, like it did with Haswell).
Also, we can see that 2 instruction set of AVX-512 SIMD are enabled only on the coprocessor Knights Landing: AVX-512 Exponential and Reciprocal Instructions (ERI) and AVX-512 Prefetch Instructions (PFI).
| CPU | SkyLake | SkyLake Xeon | CannonLake | Knights Landing | Haswell |
| SSE | ● | ● | ● | ● | ● |
| SSE2 | ● | ● | ● | ● | ● |
| SSSE3 | ● | ● | ● | ● | ● |
| SSE4.1 | ● | ● | ● | ● | ● |
| SSE4.2 | ● | ● | ● | ● | ● |
| FMA3 | ● | ● | ● | ● | ● |
| FMA4 | ○ | ○ | ○ | ○ | ○ |
| AVX | ● | ● | ● | ● | ● |
| AVX2 | ● | ● | ● | ● | ● |
| AVX512F | ○ | ● | ● | ● | ○ |
| AVX512CDI | ○ | ● | ● | ● | ○ |
| AVX512PFI | ○ | ○ | ○ | ● | ○ |
| AVX512ERI | ○ | ○ | ○ | ● | ○ |
| AVX512VLI | ○ | ● | ● | ○ | ○ |
| AVX512BW | ○ | ● | ● | ○ | ○ |
| AVX512DQ | ○ | ● | ● | ○ | ○ |
| AVX512IFMA52 | ○ | ○ | ● | ○ | ○ |
| AVX512VBMI | ○ | ○ | ● | ○ | ○ |
| SHA | ○ | ○ | ● | ○ | ○ |
| AES | ● | ● | ● | ● | ● |