Uno dei talloni d'Achille delle CPU AMD, dalla serie Phenom (Agena) alle attuali APU (Kaveri), è sicuramente la velocità della Cache, di tutti i livelli: dalla L1 fino alla L3. Rispetto alla Cache integrata nelle CPU Intel, la Cache dei processori AMD è sempre stata molto più lenta, come è possibile osservare anche in questa nostra recensione della CPU FX-8120.
Nel recente periodo AMD ha depositato diversi brevetti relativamente a nuovi metodi di gestione dei dati in Cache, così da poter velocizzare i tempi di recupero dei dati, migliorare le unità di predizione ed evitare tempi morti.
In particolare parliamo dei brevetti:
- 20140129772 (05/08/14): Prefetching to a cache based on buffer fullness - The present disclosure generally relates to processors and, more particularly, to prefetching at a processor;
- 20140115257 (04/24/14): Prefetching using branch information from an instruction cache - The present disclosure relates to processors and more particularly to prefetching for processors;
- 20140052927 (02/20/14): Data cache prefetch hints - The present invention provides a method and apparatus for using prefetch hints;
- 20130346695 (12/26/13): Integrated circuit with high reliability cache controller and method therefor - This disclosure relates generally to computer systems, and more specifically to integrated circuits for computer systems having cache controllers;
- 20130346703 (12/26/13): Data cache prefetch throttle - This application relates generally to processor-based systems, and, more particularly, to throttling data cache prefetching in processor-based systems;
- 20130311724 (11/21/13): Cache system with biased cache line replacement policy and method therefor - This disclosure relates generally to a cache s stem, and more particularly to a cache system with a cache line replacement policy;
- 20130262775 (10/03/13): Cache management for memory operations - The present invention is generally directed to computing systems. More particularly, the present invention is directed to memory operations executed in a heterogeneous computing system;
- 20130227321 (08/29/13): Method and apparatus for cache control - This invention relates to processors, and more particularly, to cache memories in processors;
- 20130227221 (08/29/13): Cache access analyzer - The present disclosure relates to software tools for efficiency analysis of a central processing unit architecture;
- 20130173834 (07/04/13): Methods and apparatus for injecting pci express traffic into host cache memory using a bit mask in the transaction layer steering tag - Embodiments of the subject matter described herein relate generally to mechanisms for implementing transaction layer processing hints in peripheral component interconnect express (PCIe)-compliant computing systems. More particularly, embodiments of the subject matter relate to the use of a bit mask in the steering tag header of the transaction layer to facilitate injecting PCIe traffic into host cache memory;
- 20130073811 (03/21/13): Region privatization in directory-based cache coherence - This application is related to cache replacement policy, and specifically to dual-granularity state tracking for directory-based cache coherence.
Una cosa singolare da notare è come questi brevetti siano stati depositati in gran numero a partire dal ritorno di Jim Keller in AMD. Nel 2011, infatti, solo due brevetti riguardanti la Cache sono stati depositati da AMD. Tra il 2012 e i primi cinque mesi del 2014, invece, sono ben 24. Evidentemente in AMD finalmente si sono accorti di quali sono i punti deboli delle proprie architetture.